InAs/Si Hetero-Junction Nanotube Tunnel Transistors

Amir N. Hanna; Hossain M. Fahad; Muhammad M. Hussain

doi:10.1038/srep09843

journal article Open Access Apr 29, 2015

InAs/Si Hetero-Junction Nanotube Tunnel Transistors

Amir N. Hanna Hossain M. Fahad Muhammad M. Hussain

Scientific Reports Vol. 5 No. 1 · Springer Science and Business Media LLC

View at Publisher Save 10.1038/srep09843

Abstract

AbstractHetero-structure tunnel junctions in non-planar gate-all-around nanowire (GAA NW) tunnel FETs (TFETs) have shown significant enhancement in ‘ON’ state tunnel current over their all-silicon counterpart. Here we show the unique concept of nanotube TFET in a hetero-structure configuration that is capable of much higher drive current as opposed to that of GAA NW TFETs.Through the use of inner/outer core-shell gates, a single III-V hetero-structured nanotube TFET leverages physically larger tunneling area while achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. Numerical simulations has shown that a 10 nm thin nanotube TFET with a 100 nm core gate has a 5×normalized output current compared to a 10 nm diameter GAA NW TFET.

Topics

No keywords indexed for this article. Browse by subject →

References

36

[1]

Ionescu, A. & Riel, H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011). 10.1038/nature10679

[2]

Loh,. Wei-Yip. . et al., Sub-60nm Si Tunnel Field Effect Transistors with Ion >100 μA/μm. Paper presented at IEEE Euro. Sol. Stat. Dev. Res. Conf., Sevilla, Spain. Sevilla: IEEE.(DOI: 10.1109/ESSDERC.2010.5618418). (2010, September).

[3]

Verhulst, A., Vandenberghe, W., Maex, K. & Groeseneken, G. Boosting the on-current of a n-channel nanowire tunnel field-effect. J. Appl. Phys. 104, 064514–064510 (2008). 10.1063/1.2981088

[4]

Verhulst, A. et al.,Complementary silicon-based heterostructure tunnel-FETs with high tunnel rates. IEEE Electron Device Lett. 29, 1398–1401 (2008). 10.1109/led.2008.2007599

[5]

Chau, R. et al. Benchmarking nanotechnology for high-performance and low-power logic transistor applications. IEEE Trans. Nanotechnol. 4, 153–158 (2005). 10.1109/tnano.2004.842073

[6]

Fahad, H. & Hussain, M. High-Performance Silicon Nanotube Tunneling FET for Ultralow-Power Logic Applications. IEEE Trans. Electron Devices. 60, 1034–1039 (2013). 10.1109/ted.2013.2243151

[7]

Fahad, H. & Hussain, M. Are nanotube architectures more advantageous than nanowire architectures for field effect transistors? Sci. Rep. 2 (2012). 10.1038/srep00475

[8]

Fahad, H., Smith, C., Rojas, J. & Hussain, M. Silicon Nanotube Field Effect Transistor with Core–Shell Gate Stacks for Enhanced High-Performance Operation and Area Scaling Benefits. Nano Lett. 11, 4393–4399 (2011). 10.1021/nl202563s

[9]

Sze, S. Physics of semiconductor devices Ch. 9 (Wiley, New York, 1981).

[10]

Lu, Y. et al., Geometry dependent tunnel FET performance-dilemma of electrostatics vs. quantum confinement. Paper presented at IEEE Device Research Conference, South Bend, IN, USA. South Bend: IEEE. (DOI:10.1109/DRC.2010.5551905 ). (2010, June). 10.1109/drc.2010.5551905

[11]

Ford, A. et al. Ultrathin body InAs tunneling field-effect transistors on Si substrates. Appl. Phys. Lett. 98, 113105–113108 (2011). 10.1063/1.3567021

[12]

Tomioka, K., Yoshimura, M. & Fukui, T. Sub 60 mV/decade Switch Using an InAs Nanowire–Si Heterojunction and Turn-on Voltage Shift with a Pulsed Doping Technique. Nano Lett. 13, 5822–5826 (2013). 10.1021/nl402447h

[13]

Hanna, A. & Hussain, M.Si/Ge hetero-structure nanotube tunnel field effect transistor. J. Appl. Phys.117, 014310–014317 (2015). 10.1063/1.4905423

[14]

Bhuwalka, K., Schulze, J. & Eisele, I. A Simulation Approach to Optimize the Electrical Parameters of a Vertical Tunnel FET. IEEE Trans. Electron Devices. 52, 1541–1547 (2005). 10.1109/ted.2005.850618

[15]

Boucart, K. & Ionescu, A. Threshold voltage in tunnel FETs: physical definition, e. x. t. r. a. c. t. i. o. n., scaling. and impact on IC design. . Paper presented at IEEE Euro. Sol. Stat. Dev. Res. Conf., Munich, Germany. Munich: IEEE. (DOI:10.1109/ESSDERC.2007.4430937). (2007, September) 10.1109/essderc.2007.4430937

[16]

Tomioka, K. & Fukui, T. Tunnel field-effect transistor using InAs nanowire/Si heterojunction. Appl. Phys. Lett. 98, 083114–083117 (2011). 10.1063/1.3558729

[17]

Choi, S., Moon, D., Kim, S., Duarte, J. & Choi, Y. Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Lett. 32, 125–127 (2011). 10.1109/led.2010.2093506

[18]

Gandhi, R., Chen, Z., Singh, N., Banerjee, K. & Lee, S. CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With ≤ 50 mV/decade Subthreshold Swing. IEEE Electron Device Lett. 32, 1504–1506 (2011). 10.1109/led.2011.2165331

[19]

Vertical Si-Nanowire <formula formulatype="inline"><tex Notation="TeX">$n$</tex></formula>-Type Tunneling FETs With Low Subthreshold Swing (<formula formulatype="inline"><tex Notation="TeX">$\leq \hbox{50}\ \hbox{mV/decade}$</tex> </formula>) at Room Temperature

Ramanathan Gandhi, Zhixian Chen, Navab Singh et al.

IEEE Electron Device Letters 2011 10.1109/led.2011.2106757

[20]

Knoll, L. et al., Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed IV and NW Scaling. Paper presented at IEEE Int. Electron Devices Meet.,Washignton, DC, USA. Washignton: IEEE. (DOI: 10.1109/IEDM.2013.6724560).(2013, December).

[21]

Woo Young, C., Park, B., Jong-Duk, L. & Tsu-Jae King, L. Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec. IEEE Electron Device Lett. 28, 743–745 (2007). 10.1109/led.2007.901273

[22]

Krishnamohan, T., Donghyun, K., Raghunathan, S. & Saraswat, K., Double gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope. . Paper presented at IEEE Int. Electron Devices Meet.,SanFrancisco,CA,USA.IEDM:IEEE.(DOI:10.1109/IEDM.2008.4796839)(2008, December).

[23]

Sung Hwan, K., Hei, K., Chenming, H. & Tsu-Jae King, L., Germanium-source tunnel field effect transistors with record high ION/IOFF. . Paper presented at IEEE Symp. on VLSI Tech., Honolulu, HI, USA. Honolulu: IEEE. (2009, June).

[24]

Riel, H. et al., InAs-Si heterojunction nanowire tunnel diodes and tunnel FETs. Paper presented at IEEE Int. Electron Devices Meet., San Francisco, CA, USA. San Francisco: IEEE.(DOI: 10.1109/IEDM.2012.6479056).(2012, December).

[25]

Schenk, A., Rhyner, R., Luisier, M. & Bessire, C., Analysis of Si,. InAs,. and Si-InAs tunnel diodes. and tunnel FETs using different transport models. . Paper presented at Int. Conf. Simul. Semicond. Processes Devices., Yokohama, Japan. Yokohama: IEEE.(DOI: 10.1109/SISPAD.2011.6035075). (2011, September). 10.1109/sispad.2011.6035075

[26]

Temperature-Dependent $I$– $V$ Characteristics of a Vertical $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ Tunnel FET

Saurabh Mookerjea, Dheeraj Mohata, Theresa Mayer et al.

IEEE Electron Device Letters 10.1109/led.2010.2045631

[27]

Dewey, G. et al. Fabrication, characterization and physics of III–V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing. Paper presented at IEEE Int. Electron Devices Meet.,Washignton, DC, USA. Washignton: IEEE. (DOI:10.1109/IEDM.2011.6131666). (2011, December). 10.1109/iedm.2011.6131666

[28]

Guangle, Z. et al. Vertical InGaAs/InP Tunnel FETs With Tunneling Normal to the Gate. IEEE Electron Device Lett. 32, 1516–1518 (2011). 10.1109/led.2011.2164232

[29]

Schmid, H. et al. Fabrication of vertical InAs-Si heterojunction tunnel field effect transistors. Paper presented at IEEE Device Research Conference., Santa Barbara, CA, USA. IEEE. (DOI: 10.1109/DRC.2011.5994479 ). (2011, June). 10.1109/drc.2011.5994479

[30]

Zhao, H. et al. Improving the on-current of In0.7Ga0.3As tunneling field-effect-transistors by p++/n+ tunneling junction. Appl. Phys. Lett. 98, 093501–093503 (2011). 10.1063/1.3559607

[31]

Tomioka, K., Yoshimura, M. & Fukui, T. Steep-slope tunnel field-effect transistors using III-V nanowire/Si heterojunction. Paper presented at IEEE Symp.. on VLSI Tech.,Honolulu,HI,USA.Honolulu:IEEE.(DOI: 10.1109/VLSIT.2012.6242454)(2012, June).

[32]

Zhou, G. et al. Novel gate-recessed vertical InAs/GaSb TFETs with record high ION of 180 μA/μm at VDS = 0.5 V. Paper presented at IEEE Int. Electron Devices Meet.,SanFrancisco,CA,USA. IEEE. (DOI:10.1109/IEDM.2012.6479154) (2012).

[33]

Zhou, G. et al. InGaAs/InP Tunnel FETs With a Subthreshold Swing of 93 mV/dec and Ratio Near. IEEE Electron Device Lett. 33, 782–784 (2012). 10.1109/led.2012.2189546

[34]

Mohata, D. et al. Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio. Paper presented at IEEE Symp. on VLSI Tech.,Honolulu,HI,USA.Honolulu:IEEE.(DOI: 10.1109/VLSIT.2012.6242457)(2012, June).

[35]

Li, R. et al. AlGaSb/InAs tunnel field-effect transistor with on-current of 78 μA/μm at 0.5 V. IEEE Electron Device Lett. 33, 363–365 (2012). 10.1109/led.2011.2179915

[36]

Yu, T., Teherani, J., Antoniadis, D. & Hoyt, J. InGa0.53As0.47- GaAs0.5Sb Quantum-Well Tunnel-FETs With Tunable Backward Diode Characteristics. IEEE Electron Device Lett. 34, 1503–1505 (2013)

Cited By

88

Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET)

Raj Kumar, Arvind Kumar · 2020

Silicon

Metrics

88

Citations

36

References

Details

Published: Apr 29, 2015
Vol/Issue: 5(1)
License: View

Authors

mmh Labs, Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47906, United States

Cite This Article

Amir N. Hanna, Hossain M. Fahad, Muhammad M. Hussain (2015). InAs/Si Hetero-Junction Nanotube Tunnel Transistors. Scientific Reports, 5(1). https://doi.org/10.1038/srep09843

InAs/Si Hetero-Junction Nanotube Tunnel Transistors

You May Also Like