Analysis and implementation of an interleaved high step‐up converter with reduced voltage stress an interleaved high step‐up DC‐DC converter with ZVS
A new symmetrical structure of the interleaved converter type is proposed in this paper to obtain high voltage gain. The proposed converter delivers a very high voltage ratio using the coupled inductor technique and switched capacitor, and all this happens at a moderate duty cycle. Furthermore, the MOSFETs have low voltage stresses. Therefore, MOSFETs with low conductivity resistance can be used to reduce the conduction losses. The input current has a small ripple because the input side uses the interleaved operation. Furthermore, zero‐current‐switching (ZCS) is obtained for MOSFETs, and the problem of reverse‐recovery for diodes is confined. Moreover, the passive clamp circuit recycles the energy of the leakage inductances which avoids high voltage spikes across the switches. Performance of the proposed converter along with the small‐signal analysis is discussed in detail. Finally, a laboratory prototype is developed with 30 V input and 400 V output to verify the proposed converter.
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- Published
- Jun 27, 2022
- Vol/Issue
- 19(1)
- License
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