Modeling and Characterization of Gate Leakage in High-K Metal Gate Technology-Based Embedded DRAM

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Details

Published: Dec 01, 2013
Vol/Issue: 60(12)
Pages: 4152-4158
License: View

Authors

M

Mohit Bajaj

IBM Semiconductor Research and Development Center, Bangalore, India

R

Rajan K. Pandey

IBM Semiconductor Research and Development Center, Bangalore, India

S

Sandip De

IBM Semiconductor Research and Development Center, Bangalore, India

N

Ninad D. Sathaye

IBM Semiconductor Research and Development Center, Bangalore, India

B

Balaji Jayaraman

IBM Semiconductor Research and Development Center, Bangalore, India

R

Rishikesh Krishnan

IBM Systems and Technology Group, Hopewell Junction, NY, USA

P

Puneet Goyal

IBM Semiconductor Research and Development Center, Bangalore, India

S

Stephen S. Furkay

IBM Semiconductor Research and Development Center, Essex Junction, VT, USA

E

Edward J. Nowak

IBM Semiconductor Research and Development Center, Essex Junction, VT, USA

S

Subramanian S. Iyer

IBM Systems and Technology Group, Hopewell Junction, NY, USA

K

Kota V. R. M. Murali

IBM Semiconductor Research and Development Center, Bangalore, India

Cite This Article

Mohit Bajaj, Rajan K. Pandey, Sandip De, et al. (2013). Modeling and Characterization of Gate Leakage in High-K Metal Gate Technology-Based Embedded DRAM. IEEE Transactions on Electron Devices, 60(12), 4152-4158. https://doi.org/10.1109/ted.2013.2285940

Modeling and Characterization of Gate Leakage in High-K Metal Gate Technology-Based Embedded DRAM

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