Topics

No keywords indexed for this article. Browse by subject →

References
18
[2]
von haartman Low-Frequency Noise in Advanced MOS Devices (2007) 10.1007/978-1-4020-5910-0
[3]
schroder Semiconductor Material and Device Characterization (2006)
[5]
rosaye "Fast and slow-state traps at the MOSFET oxide interface with a temperature dependent C-V method" Electron Devices (2003)
[6]
Atlas User Manual (2013)
[12]
neves "Influence of the gate oxide thickness on the analog performance of vertical NWTFETs with Ge Source" Proc EUROSOI (2014)
[18]
mayer "Impact of SOI, Si1–xGexOI and GeOI substrates on CMOS compatible tunnel FET performance" IEDM Tech Dig (2008)
Metrics
117
Citations
18
References
Details
Published
Apr 01, 2016
Vol/Issue
63(4)
Pages
1658-1665
License
View
Funding
Coordenação de Aperfeiçoamento de Pessoal de Nível Superior, Conselho Nacional de Desenvolvimento Científico e Tecnológico, and Fundação de Amparo à Pesquisa do Estado de São Paulo
imec’s Logic Device Program and its Core Partners
Cite This Article
Felipe S. Neves, Paula G. D. Agopian, Joao Antonio Martino, et al. (2016). Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source. IEEE Transactions on Electron Devices, 63(4), 1658-1665. https://doi.org/10.1109/ted.2016.2533360
Related

You May Also Like

GaN-on-Si Power Technology: Devices and Applications

Kevin J. Chen, Oliver Haberlen · 2017

1,550 citations

CMOS image sensors: electronic camera-on-a-chip

E.R. Fossum · 1997

943 citations

Limiting efficiency of silicon solar cells

T. Tiedje, E. Yablonovitch · 1984

731 citations