FPGA-Based Design and Implementation of a High-Performance Telemetry Transmission Architecture for Satellite Communications

Adriana N. Moreno Mercado; Víctor P. Gil Jiménez

doi:10.3390/electronics15081581

journal article Open Access Apr 10, 2026

FPGA-Based Design and Implementation of a High-Performance Telemetry Transmission Architecture for Satellite Communications

Adriana N. Moreno Mercado

Víctor P. Gil Jiménez

Electronics Vol. 15 No. 8 pp. 1581 · MDPI AG

View at Publisher Save 10.3390/electronics15081581

Abstract

This paper presents a high-performance and resource-efficient Field Programmable Gate Array (FPGA)-based architecture for satellite telemetry transmission systems. The proposed design implements a flexible channel coding chain, including Reed–Solomon (R-S) encoding, convolutional encoding, symbol interleaving, pseudo-randomization, and Attached Synchronization Marker (ASM) insertion, in accordance with CCSDS recommendations. The architecture is fully integrated and configurable, allowing dynamic selection of coding schemes without requiring structural modifications. The system is implemented on a modern FPGA platform with a 32-bit AXI4-Stream interface at 110 MHz, reaching an effective throughput of up to 1.76 Gbps. Experimental results demonstrate reliable timing with positive setup and hold margins, allowing the system to operate at approximately 130 MHz. Power consumption is measured using Switching Activity Interchange Format (SAIF)-based switching activity, providing a realistic estimate of programmable logic power consumption. The total on-chip power is about 1.77 W for individual coding modes. It rises to 1.91 W in the concatenated setup, which is the worst-case scenario. The results show that the proposed architecture efficiently uses resources, runs reliably at high speeds, and exhibits predictable power consumption. This makes it well suited for high-reliability and energy-constrained satellite communication systems. resources are used.

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Details

Published: Apr 10, 2026
Vol/Issue: 15(8)
Pages: 1581
License: View

Authors

A

Adriana N. Moreno Mercado

Departamento de Teoría de la Señal y Comunicaciones, Universidad Carlos III de Madrid, Avenida de la Universidad, 28911 Leganés, Madrid, Spain

V

Víctor P. Gil Jiménez

Departamento de Teoría de la Señal y Comunicaciones, Universidad Carlos III de Madrid, Avenida de la Universidad, 28911 Leganés, Madrid, Spain

Funding

MFOC Madrid Flight on Chip—Innovation Cooperative Projects Comunidad of Madrid—HUBS 2018/Madrid Flight on Chip

Cite This Article

Adriana N. Moreno Mercado, Víctor P. Gil Jiménez (2026). FPGA-Based Design and Implementation of a High-Performance Telemetry Transmission Architecture for Satellite Communications. Electronics, 15(8), 1581. https://doi.org/10.3390/electronics15081581

FPGA-Based Design and Implementation of a High-Performance Telemetry Transmission Architecture for Satellite Communications

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